Semiconductor device and method

ABSTRACT

An electrical device includes a semiconductor chip. The semiconductor chip includes a routing line. An insulating layer is arranged over the semiconductor chip. A solder deposit is arranged over the insulating layer. A via extends through an opening of the insulating layer to electrically connect the routing line to the solder deposit. A front edge line portion of the via facing the routing line is substantially straight, has a concave curvature or has a convex curvature of a diameter greater than a maximum lateral dimension of the via.

TECHNICAL FIELD

The present invention generally relates to techniques for designingelectrical structures such as routing lines, vias, conductor tracks andterminals in electrical devices, and more particularly to techniques forinterconnecting routing lines to vias and/or for interconnectingconductor tracks to electrical contacts such as, e.g., bond pads.

BACKGROUND

A variety of techniques are known to route electrical signals inelectrical devices. Typically, chip internal routing lines are used totransport electrical signals and/or electrical power from one locationto another location of the chip. Routing lines may be connected toconductive vias passing through an insulating layer arranged over thechip to provide interconnections to solder deposits arranged over theinsulating layer. The interconnections between the conductive viasforming part of a conductive redistribution structure (RDL) and thesolder deposits are subjected to electromigration, i.e., the transportof material caused by the current flowing through the interconnection.Electromigration may adversely effect mechanical stability of theinterconnection and lifetime of the electrical device.

Further, electromigration may occur where conductor tracks of aconductive redistribution structure connect to electrical contact pads.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of embodiments and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments andtogether with the description serve to explain principles ofembodiments. Other embodiments and many of the intended advantages ofembodiments will be readily appreciated as they become better understoodby reference to the following detailed description.

The elements of the drawings are not necessarily to scale relative toeach other. Like reference numerals designate corresponding similarparts;

FIG. 1 is a schematic cross-sectional view of an interconnection betweena routing line, a via and a solder deposit of an electrical device inaccordance with one embodiment;

FIG. 2 is a schematic top view of an interconnection between a routingline, a via and a solder deposit of an electrical device in accordancewith one embodiment;

FIG. 3 is a schematic top view of an interconnection between a routingline, a via and a solder deposit of an electrical device in accordancewith one embodiment;

FIG. 4 is a schematic top view of an interconnection between a routingline, a via and a solder deposit of an electrical device in accordancewith one embodiment;

FIG. 5 is a schematic top view of an interconnection between a routingline, a via and a solder deposit of an electrical device in accordancewith one embodiment;

FIG. 6 is a schematic top view of an interconnection between a routingline, a via and a solder deposit of an electrical device in accordancewith one embodiment;

FIG. 7 is a schematic top view of an interconnection between a routingline, a via and a solder deposit of an electrical device in accordancewith one embodiment;

FIG. 8 is a schematic top view of an interconnection between a routingline, a via and a solder deposit of an electrical device in accordancewith one embodiment;

FIG. 9 is a schematic top view of an interconnection between a routingline, a via and a solder deposit of an electrical device in accordancewith one embodiment;

FIG. 10 is a schematic cross-sectional view of an electrical device inaccordance with one embodiment;

FIG. 11 is a schematic cross-sectional view of an electrical device inaccordance with one embodiment;

FIG. 12 is a schematic top view of an interconnection between aconductor track and a bond pad of an electrical device in accordancewith one embodiment;

FIG. 13 is a schematic top view of an interconnection between aconductor track and a bond pad of an electrical device in accordancewith one embodiment;

FIG. 14 is a flowchart of an embodiment of a method of manufacturing anelectrical device; and

FIG. 15 is a flowchart of an embodiment of a method of manufacturing anelectrical device.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

It is to be understood that the features of the various exemplaryembodiments described herein may be combined with each other, unlessspecifically noted otherwise.

As employed in this specification, the terms “coupled” and/or“electrically coupled” are not meant to mean that the elements must bedirectly coupled together unless stated otherwise. Intervening elementsmay be provided between the “coupled” or “electrically coupled”elements.

Some of the electrical devices described herein contain one or moresemiconductor chips. The semiconductor chips may be of different types,may be manufactured by different technologies and may include, forexample, integrated electrical, electro-optical or electro-mechanicalcircuits and/or passives. The semiconductor chips may, for example, bedesigned as logic integrated circuits, analog integrated circuits, mixedsignal integrated circuits, power integrated circuits, memory circuitsor integrated passives. They may include control circuits,microprocessors or microelectromechanical components. The semiconductorchips need not be manufactured from specific semiconductor material, forexample, Si, SiC, SiGe, GaAs, AlGaAs and, furthermore, may containinorganic and/or organic materials that are not semiconductors, such as,for example, insulators, plastics or metals.

Some of the electrical devices described herein comprise a semiconductorchip having chip internal routing lines which allow electricalconnections to be made between integrated circuits of the semiconductorchip and chip external electrical components. The routing lines may bemade of a conductive material such as, e.g., a metal. Any desired metalor metal alloy, for example, aluminum or copper, may be used as thematerial. The routing lines need not be homogenous or manufactured fromjust one material, that is to say various compositions andconcentrations of the materials or layers of different materialscontained in the routing line are possible. The routing lines arearranged within a semiconductor chip to form part of the internal chipwiring. By way of example, the routing lines may be formed in theso-called last metal layer of the semiconductor chip. A line section ofthe routing lines may have, for example, the form of a curved orstraight line or stripe. Semiconductor processing technologies may beapplied to generate and/or structure the routing lines.

In one embodiment, an insulating layer may be arranged over thesemiconductor chip. The insulating layer may comprise a hard passivationlayer and/or a polymer layer. The hard passivation layer may, e.g., bemade of an oxide or nitride layer covering the bare semiconductormaterial surface. The polymer layer may, e.g., be made of a photoresistor of any other etching resist. The insulating layer may be used toelectrically insulate a section of the routing line against, e.g., anelectrically conductive layer covering the insulating layer. Theinsulating layer may comprise an opening for the via. Thin-filmtechnologies may be applied to generate and/or structure the insulatinglayer.

An electrically conductive layer may be arranged above the insulatinglayer. The conductive layer may form part of a conductive redistributionstructure (RDL). The conductive layer may be structured to compriseelectrical contact pads and/or conductor tracks. It may, e.g., comprisemetal, metal alloy or a conducting polymer material. A furtherinsulating layer overlaying the conductive layer may be used as a solderstop layer.

Insulating layer(s) and/or conductor track(s) and/or electrical contactpad(s) and/or via(s) may be applied during wafer level processing, thatis during frontend processing. By way of example, a polymer layer may beapplied by a CVD (Chemical Vapor Deposition) process or by a spincoating process. The polymer layer may be made of a photoresist or ofany other etching resist. Conductor track(s) and/or via(s) and/orelectrical contact pad(s) may be formed from one or more conductivelayers. In one embodiment, a conductive layer may comprise a seed layerand a further layer which is galvanically deposited (“plated”) onto theseed layer. In one embodiment, an electroless plating process such aselectroless nickel-palladium plating may be used. Electroless plating isalso referred to as chemical plating in the art. Further, otherdeposition methods such as physical vapor deposition (PVD), chemicalvapor deposition (CVD), sputtering, spin-on processes, spray depositionor printing such as, e.g., screen printing or ink-jet printing may beemployed to form the conductive layer(s). The structuring of theconductive layer(s) to form the via(s) and/or electrical contact pad(s)and/or conductor tracks may be performed during deposition or later byapplying appropriate structuring methods.

The electrical devices described herein may comprise an insulating layerand a via extending through an opening of the insulating layer toelectrically connect to the routing line. The via may be formed of asingle opening or hole. The via is electrically conductive, i.e.electrical signals or electrical power may be transferred through thevia. To this end, the one or more holes forming the via may be filled orcoated with an electrically conducting material. The electricallyconducting material passing the via may be composed of any desiredelectrically conducting material, for example, of a metal, such ascopper, aluminum, titanium, gold, silver, palladium, platinum, nickel,chromium, or nickel vanadium, a metal alloy, solder, or an electricallyconducting organic material. Vias as described herein may form part of aredistribution structure (RDL) comprising one or more structuredconducting layers separated by polymer layers and interconnected by thevias.

The electrical devices described herein may include electrical contactpad(s) such as, e.g., bond pads. The electrical contact pad(s) mayrepresent the external terminals of the electrical device. They may beaccessible from outside the electrical device and may thus allowelectrical contact to be made with electrical component(s) of theelectrical device such as, e.g., semiconductor chip(s) from outside ofthe device. In one embodiment, the electrical contact pad(s) may be bondpads, for instance bond pads of a device package. In one embodiment, theelectrical contact pad(s) may be bond pads on which solder deposits areplaced, e.g., so-called “ball pads”. Such solder deposits may thenrepresent the external terminals of the electrical device.

Furthermore, the electrical contact pad(s) may be thermally conductiveand may serve as heat sinks for dissipating the heat generated by thecomponent(s) of the electrical device. The electrical contact pad(s) maybe composed of any desired electrically conductive material, forexample, of a metal, such as copper, aluminum or gold, a metal alloy oran electrically conductive organic material.

FIG. 1 is a schematic cross-sectional view of a part of an electricaldevice 100 in accordance with one embodiment. A routing line 103 made ofan electrically conducting material such as, e.g., a metal or a metalalloy extends in a semiconductor chip 104. The routing line 103 formspart of the internal wiring (not further illustrated) of thesemiconductor chip 104. The internal wiring may interconnect the routingline 103 to an integrated circuit (not illustrated) implemented in thesemiconductor chip 104. The routing line 103 may be structured from theso-called last metal of the internal wiring of the semiconductor chip104, i.e., the uppermost metal layer integrated within the semiconductorchip 104.

A layer 101 of an insulating material is arranged over an upper surface106 of the semiconductor chip 104 and over the routing line 103. Theinsulating layer 101 may be made of one or more dielectric materials. Byway of example, it may comprise one or more of a hard passivation layerand a polymer layer. In one embodiment, the upper surface 106 of thesemiconductor chip 104 may abut and directly contact the insulatinglayer 101. In one embodiment, the insulating layer 101 may abut anddirectly contact the routing line 103.

A via 107 extends through the insulating layer 101. The via 107 iselectrically conductive. The via 107 electrically connects to therouting line 103. The via 107 may be implemented by a recess or outcut108 of the insulating layer 101. The recess or outcut 108 is filled withor the walls of the recess or outcut 108 is coated with an electricallyconducting material such as, e.g., a metal, a metal alloy, solder, or anelectrically conducting polymer.

An electrical contact pad 150 may be arranged over the insulating layer101 and over the outcut 108 thereof containing the via 107. Thus, thevia 107 may electrically connect the electrical contact pad 150 to therouting line 103. The electrical contact pad 150 may be made of anelectrically conducting material such as, e.g., a metal, a metal alloy,solder, or an electrically conducting polymer. The electrical contactpad 150 may extend directly on an upper surface 102 of layer 101.

As illustrated by way of example in FIG. 1, the via 107 and theelectrical contact pad 150 may be formed of one and the same conductivelayer. In this case, the via 107 and the electrical contact pad 150 aremade of the same material(s) and are integral, i.e., the via 107 can beconsidered to form an integral part of the electrical contact pad 150.That way, the via 107 and the electrical contact pad 150 may bemanufactured by the same deposition process(es). However, it is alsopossible that the via 107 and the electrical contact pad 150 are made ofdifferent materials and are manufactured in separate processes, e.g., byfirst filling the outcut 108 with a via metal and then plating theelectrical contact pad 150 with a contact pad metal, which may bedifferent from the via metal.

A solder deposit 160 such as, e.g., a solder bump or solder ball may bearranged over the insulating layer 101 and attached to the electricalcontact pad 150. The solder deposit 160 may represent an externalterminal of a package accommodating the semiconductor chip 104. Thesolder deposit may have a maximum lateral dimension or diameter of D. Adielectric layer 130 may be arranged over the conductive layer of whichthe electrical contact pad 150 is formed. The dielectric layer 130 mayhave an opening to expose the electrical contact pad 150. Thus, thedielectric layer 130 may serve as a solder stop layer. It may be made ofthe same material(s) as the insulating layer 101. The routing line 103,the insulating layer 101, the electrical contact pad 150, the solderdeposit 160 and the dielectric layer 130 may each be in direct contactto the respective adjacent layer(s) or structures, or may be separatedby intermediate layers such as, e.g., adhesion layers, or by multiplepolymer and/or conductive layers of a multi-layer RDL from therespective adjacent layer(s) or structures.

The via 107 is configured to transport electrical current between therouting line 103 and the solder deposit 160. Current flowing between therouting line 103 and the solder deposit 160 tends not to use the entirearea offered by the via 107. Rather, the current prefers a “shortest”path in the vicinity of a front edge 109 of the via 107 as illustratedby the arrow 110. The front edge 109 of the via 107 is defined by aportion of the outline of the via 107 within a plane defined by theupper surface 102 of the insulating layer 101, with the portion facingthe direction of the routing line 103 from which the current arrives.That is, the front edge 109 of the via corresponds to an edge of theoutcut 108 of the insulating layer 101. In FIG. 1, the current flowsfrom the right hand side of the routing line 103 to the left hand side,and therefore, the front edge 109 of the via 107 corresponds to theright hand side edge of the outcut 108.

In other words, an electrical device 100 as illustrated in FIG. 1 mayexhibit a zone of high current density in the vicinity of front edge 109and the arrow 110. Such zone of high current density may cause enhancedelectromigration at the interface between the via 107 and the solderdeposit 160 and may limit the life time of the electrical device 100.

It is to be noted that the electrical conductivity of solder istypically lower than the electrical conductivity of the material ofwhich the electrical contact pad 150 is made. By way of example, theelectrical conductivity of the solder of solder deposit 160 may be atleast five times lower than the electrical conductivity of the materialof which the electrical contact pad 150 is made. The smaller thevertical dimension H (height or thickness) of the electrical contact pad150, the more current density enhancement (relative to the nominalcurrent density on the assumption of a constant current densitydistribution across the interface area) and electromigration is to beexpected. An interface cross section area 111 of the via 107 is definedby a peripheral line of the outcut 108 in the insulating layer 101, i.e.a section of the conductive via 107 through a plane defined by the uppersurface 102 of the insulating layer 101. A horizontal dimension of theinterface cross section area 111 of the via 107 in the direction of therouting line 103 is denoted by L (length). In FIG. 1, by way of example,the thickness H of the electrical contact pad 150 corresponds to thethickness of the insulating layer 101, and therefore, outcut 108 of theinsulating layer 101 is filled up to the plane defined by the uppersurface 102 of the insulating layer 101 with conductive material. Ingeneral, however, the thickness H of the electrical contact pad 150 maybe smaller or greater than the thickness of the insulating layer 101.Further, the thickness H of the electrical contact pad 150 may beapproximately constant across the entire extension of the contact padinside and outside of the outcut 108.

FIGS. 2-9 illustrate top views of the device 100 according to variousembodiments, the electrical devices in FIGS. 2-9 are denoted byreference numbers 200, 300, 400, 500, 600, 700, 800, 900. In allembodiments electromigration is reduced by virtue of a specific designof the via 107 (or, correspondingly, outcut 108) and/or a specificdesign of the routing line 103 or both. All FIGS. 2-9 illustrate the topview outline of the routing line 103, the top view outline of theinterface cross section area 111 of the via 107 and the top view outlineof the solder deposit 160 of diameter D. Thus, in other words, FIGS. 2-9may be interpreted to illustrate the solder deposit 160, the electricalcontact pad 150 and the layer 101 of an insulating material astransparent structures under which the interface cross section area 111of via 107 and the routing line 103 are visible. Further, it is to benoted that in FIGS. 2-9 a notation of reference numbers is chosen todenote structurally identical or similar parts with reference numbers ofconforming last two digits. Thus, reference numbers having identicallast two digits designate corresponding similar parts and thedescription of any one of these parts may apply to the similar partsshown in other figures if not stated otherwise or technically excluded.

According to FIG. 2, routing line 203 (corresponding to routing line103) may be composed of a line section 203 a and a contact section 203b. The line section 203 a may, e.g., have an elongated shape such as theshape of a line or a stripe. The width W of the line section 203 a ofthe routing line 203 may be more or less constant along the extension ofthe line. By way of example, the width W of the line section 203 a maybe about a few, ten, or some tens of μm, e.g., 5 μm-70 μm, or 20 μm-50μm, or about 35 μm. By way of example, the line section 203 a of therouting line 203 may be a signal or power line implemented in the lastmetal wiring layer of an integrated circuit (IC) formed in thesemiconductor chip 104. Instead of a line, an IC-via array of same widthW can be used also.

The lateral dimension or width W of the routing line 203 increases whenthe routing line 203 approaches the via 207. More specifically, asillustrated in FIG. 2, a contact section 203 b of an increasing width ofthe routing line 203 starts where the line section 203 a ofsubstantially constant width W ends. In the embodiment shown in FIG. 2,the contact section 203 b may continually increase in width towards afront edge 209 (corresponding to front edge 109) of the via 207.

The contact section 203 b may have a first portion connecting to theline section 203 a defined by two edges departing from each other underan angle α of, e.g., about 50-180°, more particularly 80-150°, e.g.,about 90°. By way of example, the contact section 203 b may have asquare or quadratic shape with the line section 203 a of the routingline 203 connecting to a corner of the square or quadratic contactsection 203 b. The expanding width W of the routing line 203 allows thecurrent to homogeneously distribute over a large lateral area whenhitting the via 207 at the vertical projection of the front edge 209facing the line section 203 a of the routing line 203.

Via 207 may have a specific design. By way of example, the via 207 mayhave a triangular shape. As illustrated in FIG. 2, the via 207 may havea front edge 209 facing the line section 203 a of the routing line 203.The front edge 209 may, e.g., be shaped as a substantially straightline. The front edge 209 may be orientated substantially in aperpendicular direction to the main direction of current flow, which maycorrespond to the axis of the line section 203 a and/or to the axis ofthe contact section 203 b of the routing line 203. In one embodiment,the axis of the line section 203 a and the axis of the contact section203 b are collinear and are both represented by axis A-A as shown inFIG. 2. Axis A-A may also correspond to the main direction of currentflow and further corresponds to the cross-sectional axis of FIG. 1.Generally, the axis of the line section 203 a and the axis of thecontact section 203 b need not to be collinear but may be parallel orinclined to each other. Further, line section 203 a of the routing line203 must not necessarily connect to the contact section 203 b of therouting line 203 at a corner thereof.

The front edge 209 of the via 207 runs from two corners or bends of thetriangle and may have a length X. X may correspond to the maximum widthof the via 207 at the interface cross section area 211, if the maximumwidth of the via 207 occurs along the length of the front edge 209 as,for instance, shown in FIG. 2. The front edge 209 may be arrangedperpendicular to the dimension of (maximum) length L of the interfacecross section area 211.

A maximum width Wm of the routing line 203, more specifically, of thecontact section 203 b of the routing line 203, may be greater than thelength X of the front edge 209. In one embodiment, e.g., as shown inFIG. 2, a line of maximum width Wm of the routing line 203 may coincidewith a line defined by the front edge 209. In one embodiment the line ofmaximum width Wm may intersect or extend in the vicinity of the(straight or curved) line defined by front edge 209.

The length L of via 207 may be smaller than the length X of the frontedge 209. The line defined by the maximum lateral dimension (in FIG. 2length X) of the via 207 at the interface cross section area 211 may beoriented perpendicular to the line of minimum lateral dimension of thevia 207 at the interface cross section area 211.

Due to the shape of the contact section 203 b of the routing line 203and/or the shape of the via 207 at the interface cross section area 211,current flowing from the routing line 203 into the via 207 and from thevia 207 into the solder deposit 260 is offered plenty of space in alateral direction to homogeneously distribute across the length X offront edge 209. That way, the sheet current density at each point acrossthe front edge 209 is considerably low. As compared to a standard via ofthe same interface area but having a circle-shaped outline, the maximumsheet current density may be reduced, e.g., from about 450 A/mm² toabout 200 A/mm² at the front edge 209 of via 207. Thus, electromigrationbetween the via and the solder is minimized. Ideally, the front edge 209extends along a line with identical sheet current density. In this case,the front edge 209 may have a concave curvature similar to FIG. 6.

By way of example, for all embodiments if not mentioned otherwise, thelength L may be between 5 and 100 μm, more particularly between 10 and50 μm and, e.g., about 25 μm. The length X may be greater than 50 μm,e.g., between 50 and 300 μm, more particularly greater than 100 μm,e.g., between 100 and 200 μm, and, e.g., about or greater than 150 μm.The lateral dimension or diameter D of the solder deposit may be between50 and 350 μm, more particularly between 150 and 300 μm and, e.g., about250 μm.

FIG. 3 illustrates a schematic top view of an embodiment interconnectionbetween a routing line 303 and via 307 of an electrical device 300 inaccordance with one embodiment. The cross-sectional view shown in FIG. 1of electrical device 100 is also a cross-sectional view of device 300shown in FIG. 3. Further, the routing line 303 containing the linesection 303 a and the contact section 303 b may be formed and designedin a manner identical to the routing line 103, 203 shown in FIGS. 1 and2. The via 307 is identical to vias 107, 207 except that via 307 has arectangular cross-section through the first surface 102 of theinsulating layer. Consequently, the interface cross section area 311 ofvia 307 has a rectangular shape. The dimensions L, X of the interfacecross section area 311 and the dimensions W and Wm of the routing line303 may be the same as mentioned above with reference to FIGS. 1 and 2.

Front edge 309 of via 307 is defined by a portion of the outline of theinterface cross section area 311 between two corners or bends thereof,with the portion facing the direction of main current flow in therouting line 303. Again, the front edge 309 is a substantially straightline having, e.g., a length of X and, e.g., extending along the maximumwidth of the via 307 at the interface cross section area 311.

FIG. 4 illustrates a schematic top view showing routing line 403 and avia 407 of an electrical device 400 in accordance with one embodiment. Across-sectional view of electrical device 400 along line A-A isillustrated in FIG. 1 and may be identical to the cross-sectional viewalong lines A-A of the embodiments described above.

The routing line 403 may comprise a line section 403 a and a contactsection 403 b. The line section 403 a and the contact section 403 b maybe identical to the line sections 103 a, 203 a, 303 a and the contactsections 103 b, 203 b, 303 b, respectively, of the aforementionedembodiments.

The via 407 may be identical to the vias 107, 207, 307 as describedabove except that via 407 has a half-round or arcuate shapedcross-section area 411 through the upper surface 102 of the insulatinglayer 101. The dimensions L, X of the interface cross section area 411and the dimensions W and Wm of the routing line 403 may be the same asin the aforementioned embodiments.

In accordance with the aforementioned embodiments, a front edge 409 ofvia 407, which may face the line section 403 a of the routing line 403and may extend over the full width of the interface cross section area411, may be shaped as a substantially straight line having a length X.Another edge portion of via 407 at the interface cross section area 411opposite to the front edge 409 may have an arcuate shape.

According to FIG. 5, a routing line 503 may have a line section 503 aand a contact section 503 b. The line section 503 a may be manufacturedand shaped identical to the line sections 103 a, 203 a, 303 a and 403 aas described above. The contact section 503 b may have a rectangular orsquare shape. All further particulars described above in relation to therouting lines 103-403 may also be applied to routing line 503, exceptthat in this example the line section 503 a connects to the contactsection 503 b at about a mid-point of one side of the contact section503 b rather than at a corner thereof. FIG. 1 illustrates across-section of electrical device 500 along line A-A as shown in FIG.5.

Via 507 may have a predominantly rectangular or quadratic shape with anarcuate recess being provided at the side of the via 507 which faces theline section 503 a of the routing line 503. The arcuate recess defines afront edge 509 which runs from two corners or bends of the outline ofthe interface cross section 511 and may have a length X. The dimensionsL, X, W, Wm may be identical to the corresponding dimensions of theaforementioned embodiments. Ideally, the front edge 509 extends along aline with identical sheet current density. In this case, the front edge509 may have a concave curvature similar to FIG. 6.

As already depicted in other figures illustrating a top view of aninterconnection between a routing line, a via and a solder deposit, thefront edge 509 of via 507 at the interface cross section area 511defines a transition line for current flowing between the via 507 andthe solder deposit 560, where electromigration is reduced due to theconcave curvature of front edge 509 and the considerable length X overwhich the current flow may distribute to reduce the sheet currentdensity.

In other words, front edge 509 of the via 507 faces the line section 503a of the routing line 503. Thus, the front edge 509 has an arcuate,curved, semicircular, or semi-oval shape, allowing the current todistribute over a wide lateral area before entering the via 507 and onleaving the via 507 to enter the solder deposit 560. The length X of thearcuate, curved, semicircular, or semi-oval edge 509 may, e.g., beapproximately the same as the maximum lateral dimension of the via 507,or may even be greater. Other particulars of electrical device 500 maybe identical to the corresponding particulars of other embodimentsdescribed herein and the description thereof is omitted for the sake ofbrevity.

By way of example, employing a front edge 509 of semicircular shape asshown in FIG. 5, i.e., an equal distance from the end of the linesection 503 a to the front edge 509 of the via 507, allows for a sheetcurrent density reduction by a factor of 4 at the front edge 509compared to a standard via of the same interface cross section area buthaving a circle-shaped outline.

According to FIG. 6, in one embodiment an electrical device 600 mayfeature an interface cross section area 611 of via 607 having an overallshape similar to a semi-circle or semi-oval. Accordingly, in thisembodiment the length L may be smaller than in the embodiments describedabove. The length X of the front edge 609 of via 607 at the interfacecross section area 611 may be similar to the corresponding dimensions Xof aforementioned embodiments. By way of example, the routing line 603may have a line section 603 a and a contact section 603 b, the linesection 603 a and the contact section 603 b having the same shape as theline section 503 a and the contact section 503 b of the electricaldevice 500. Further, similar to the electrical device 500, the via 607has a front edge 609 defined by a portion of the outline of the via 607which faces the main direction of current flow, e.g., the line section603 a of the routing line 603. The front edge 609 has a concavecurvature. It may have a shape similar to the shape of a semi-circle ora semi-oval. Other types of arcuate shapes are also possible. Similarlyto the embodiment shown in FIG. 5, the current, when leaving the linesection 603 a of the routing line 603 and flowing towards the via 607,may distribute over a wide spatial and longitudinal area before enteringthe via 607, so that the sheet current density at the front edge 609,when leaving the via 607 and entering the solder deposit 660, isreduced. Ideally, the front edge 609 extends along a concave line withidentical sheet current density.

By way of example, shaping the via 607 to a semi-oval stripe as shown inFIG. 6, with a longitudinal dimension greater than the lateral dimensionallows for a current density reduction by a factor of about 10 comparedto a standard via of the same interface cross section area but having acircle-shaped outline.

FIG. 7 is a schematic top view of an electrical device 700 having arouting line 703 and a via 707, the interface cross section area beingdenoted by reference numeral 711. The routing line 703 may comprise aline section 703 a and a contact section 703 b, which have already beendescribed with reference to aforementioned embodiments. The via 707 mayhave a front edge 709 facing the line section 703 a of the routing line703. Similar to the embodiments illustrated in FIGS. 2-4, the front edge709 is designed as a substantially straight line oriented substantiallyperpendicular to an axis of the line section 703 a of the routing line703. Here, by way of example, the length X of the front edge 709 isidentical to the maximum lateral dimension of the via 707 at theinterface cross section area 711. However, in one embodiment, the lengthX of the front edge 709 may be greater than the maximum lateraldimension of via 707, e.g., if the front edge 709 has a curved shape as,e.g., illustrated in FIGS. 5 and 6. The electrical device 700 shown inFIG. 7 may be similar or identical to the electrical devices 100, 200shown in FIGS. 1 and 2 with the exception that one or more of thecorners of the triangle-shaped interface cross section area 711 are cut.

According to FIG. 8, the corners of interface cross section area 811 maybe rounded. In FIG. 8, the contact section 803 b and the line section803 a of the routing line 803 may be similar to aforementionedembodiments, see, e.g., FIG. 7. The front edge of the via 807 at theinterface cross section area 811 is denoted by reference numeral 809 andmay be implemented, e.g., by a straight line (see FIG. 8) runningbetween two bends of the outline of the interface cross section area 811or by a curved line as depicted, e.g., in FIG. 5 or 6. All dimensions W,Wm, X, L may have similar or identical values as in the aforementionedembodiments.

Further, it is to be noted that specific shapes of vias 107, 207, 307,407, 507, 607, 707, 807 and routing lines 103, 203, 303, 403, 503, 603,703, 803 may be mixed or interchanged throughout the various embodimentsshown in FIGS. 1-8. In all embodiments, corners of the via at theinterface at the interface cross section area may be cut or roundedsimilar to the embodiments illustrated in FIGS. 7 and 8.

In one embodiment which is not illustrated by a Figure, the front edgeportion of the via at the interface cross section area may have a slightconvex curvature. A slight convex curvature may, for example, be acurvature of a diameter greater than a maximum lateral dimension of thevia or a curvature of a diameter greater than a maximum lateraldimension Wm of the routing line or a curvature of a diameter greaterthan a maximum lateral dimension D of the solder deposit. It is to benoted that a convex curvature of the front edge portion of the via tendsto concentrate the current and therefore, in order to maintain smallsheet current densities at the front edge of the via, only slightlyconvex curvatures (at least less than the curvature of a circular via)should be provided.

FIG. 9 illustrates a schematic top view of an electrical device 900according to one embodiment. A routing line 903 comprises a line section903 a and a contact section 903 b, with the line section 903 a directlyconnecting to a corner of the contact section 903 b. For sake ofbrevity, reference is made to the corresponding description inconjunction with FIGS. 1-4.

Multiple vias 907 a, 907 b, 907 c, 907 d are designed to extend throughmultiple openings in the insulating layer 101 (see FIG. 1), theinterface cross section areas thereof in the plane defined by the uppersurface 102 of the insulating layer 101 are denoted by referencenumerals 911 a, 911 b, 911 c and 911 d, respectively. The multiple vias907 a, 907 b, 907 c, 907 d are arranged in a pattern, with an outline ofthe pattern having, e.g., a polygonal shape. By way of example, as shownin FIG. 9, the outline of via pattern may have a square shape. Referencenumeral 909 denotes a front side of the polygon (e.g., of a square asshown in FIG. 9) facing the line section 903 a of routing line 903. Alongitudinal direction or axis of the line section 903 a of routing line903 may be aligned to a mid-point of the side 909 of the polygon facingthe line section 903 a. An orientation of the axis of the line section903 a perpendicular to the side 909 of the polygon (square) facing theline section 903 a allows the current flowing from or into the routingline 903 to distribute over a comparatively large spatial area whenhitting the via pattern. FIG. 9 displays a phantom line CC of constantsheet current density and illustrates that this line approximatelymatches to the geometry and orientation of the via pattern. In this way,electromigration is minimized at the interface cross section areas 911a, 911 b, 911 c, 911 d.

In other words, the design of multi vias 907 a, 907 b, 907 c, 907 d andthe design of the routing line 903 may be characterized in that thepolygonal (square) outline of the via pattern is rotated in relation tothe rectangular outline of the contact section 903 b of routing line 903by a rotating angle of 45°. The lateral dimension X at the front sidemulti vias 907 b, 907 d as seen from the routing line 903 is of mainimportance for the reduction of the maximum sheet current density andcould be increased by providing more than two vias (e.g., more than 3, 4or 5 vias). The backside multi vias 907 a, 907 b could be omitted.Further, the line section 903 a may connect to the contact section 903 bof the routing line 903 at a corner thereof.

It is to be noted that multiple vias may also be arranged in an arcuaterow to follow a concave line such as, e.g., the phantom line CC ofconstant sheet current density. In this case, the front edge patternline portion of the outline of the via pattern may have a concave shape.In FIG. 9, the front side multi vias 907 b, 907 d follow such a concaveline, namely the phantom line CC. In general, more than two vias (e.g.,more than 3, 4 or 5 vias) may be arranged in an arcuate row to follow aconcave line such as, e.g., the phantom line CC of constant sheetcurrent density in order to reduce the maximum sheet current density.Such front side vias arranged in an arcuate row may form the entirepattern or may be supplemented by backside vias also arranged in anarcuate row within the pattern.

In electrical device 900, all dimensions W, Wm, X, L may have values asdescribed before in relation to other embodiments. Further, FIG. 1 maybe interpreted as a cross-section of the electrical device 900 alongline A-A with the exception that the multi via 907 a, 907 b, 907 c, 907d does not intersect with line A-A and should thus not be visible inFIG. 1 when taken in combination with FIG. 9.

It is to be noted that in electrical devices 100-900, the contactsection of the routing line must not necessarily overlap the whole areaor even a partial area of the interface cross section areas in FIGS.2-9. In some embodiments, the contact section of the routing line mayend at or near the “beginning” of the via, i.e., near to the projectionof the front edge of the via. Since the effect of electromigration ismainly confined to the front edge of the via, it can be sufficient togeometrically design the via and/or the part of the contact sectionwhich extends between the end of the line section and the front edge inaccordance with the above teaching.

Further, it is to be noted that in electrical devices 100-900, the viasmay have vertical walls. That is, the interface cross section areasdepicted in FIGS. 2 to 9 (which are defined by a section through thevias in a plane defined by the upper surface 102 of the insulating layer101) may correspond to the interface areas between the contact sectionof the routing lines and the vias.

FIG. 10 is a schematic cross-sectional view of an electrical device 1000in accordance with one embodiment. Electrical device 1000 may be animplementation of any of the electrical devices 100 to 900 as describedabove. Vice versa, details described in conjunction with electricaldevice 1000 may likely apply to electrical devices 100 to 900.Electrical device 1000 may comprise a semiconductor chip 1004 comprisinga routing line 1003. The upper surface 1006 of the semiconductor chip1004 may be coated with a hard passivation layer 1020. The hardpassivation layer 1020 may, e.g., be made of an oxide or nitride layercovering the bare semiconductor material surface. The hard passivationlayer 1020 may have an opening 1021 exposing a portion of the routingline 1003.

A polymer layer 1001 may be arranged over the hard passivation layer1020. The polymer layer 1001 may be made of an etch resist and/or anepoxy-based material. By way of example, the polymer layer 1001 may bemade of a photoresist such as, e.g., SU8 which is epoxy-based. Thepolymer layer 1001 may be electrically insulating and/or photosensitiveand/or filled by a filler material and may, for example, containpolyimide, silicone, polyurethane, parylene or other appropriatematerials.

A conductive layer structured to an electrical contact pad 1050 isarranged over the polymer layer 1001. The conductive layer 1003 maycomprise any of the materials and have any of the dimensions and shapesof the conductive layer as described herein with reference to theaforementioned embodiments.

The polymer layer 1001 comprises an opening 1008 containing anelectrically conducting via 1007. The via 1007 may be made of any of thematerials and may have any of the dimensions and the shapes as describedin the aforementioned embodiments. In particular, the via 1007 may formpart of the conductive layer 1003 and may be manufactured by a platingprocess.

A dielectric layer 1030 may be deposited on top of the conductive layerstructured into the electrical contact pad 1050. The dielectric layer1030 may, for instance, be deposited from a gas phase or from asolution, or can be laminated onto the conductive layer forming theelectrical contact pad 1050 and the polymer layer 1001. The dielectriclayer 1030 may be fabricated from a polymer, such as parylene,photoresist material, imide, epoxy, duroplast, silicone, siliconenitride or an inorganic, ceramic-like material, such as silicon-carboncompounds.

The dielectric layer 1030 may have an opening 1031 to expose a portionof the conductive layer structured to the electrical contact pad 1050.The opening 1031 may, for example, be produced by usingphotolithographic methods, ablation and/or etching methods. The exposedportion of the structured conductive layer serves as the electricalcontact pad 1050. The electrical contact pad 1050 may be an externalcontact pad or bond pad of a package in which the semiconductor chip1004 is accommodated.

The conductive layer structured to the electrical contact pad 1050 andthe dielectric layer 1030 may form a so-called redistribution structure(RDL). The RDL may not only contain one but a plurality of conductivelayers separated by a plurality of intermediate polymer layers toimplement a multi-layer RDL. Such RDL may be fabricated by well-knownthin-film technology processes and my additionally provide a flexiblesignal or power routing through conductor tracks and a design of the(external) electrical contact pads 1050 (that is, e.g., the packageterminals) tailored to the customer's needs.

A solder deposit 1060 such as, e.g., a solder bump or solder ball may beattached to the electrical contact pad 1050. The solder deposit 1060 mayrepresent an external terminal of a package accommodating thesemiconductor chip 1004 or any other electrical component. Thepassivation layer 1020, the polymer layer 1001, the conductive layer1003 structured to the electrical contact pad 1050 and the dielectriclayer 1030 may each be in direct contact with each other or may beseparated by intermediate layers such as, e.g., adhesion layers, etc.

A thickness T of the dielectric layer 1030 (e.g., solder stop layer) maytypically be up to 10 μm or even higher. The thickness H of theelectrical contact pad 1050 may be smaller than 15 μm, more particularly10 μm and still more particularly 8 μm. Similarly, the height of the via1007 may be smaller than 15 μm, more particularly 10 μm and still moreparticularly 8 μm. It is to be noted that increasing the thickness H ofthe electrical contact pad 1050 or the height of the via 1007 is anexpensive measure and therefore, a small thickness/height is typicallyenvisaged. The polymer layer 1001 may typically have a thickness ofabout 8 μm. The hard passivation layer 1020 may typically have athickness of about 1 μm. The routing line 1003 may typically have athickness of about 0.5 to 3 μm. Dimensions of D, L have already beenmentioned above.

According to one embodiment as shown in FIG. 11, an electrical device2000 comprises a structure 2070 having an upper surface 2002. Thestructure may, e.g., be any kind of substrate for supporting an RDL. Itmay, e.g., comprise a semiconductor chip 2004 and an insulating layer2001, wherein the upper surface of the insulating layer 2001 forms theupper surface 2002 of the structure 2070. In this case, the abovedescription of dimensions, materials and other characteristics of thesemiconductor chip and/or the layer of an insulating material of theaforementioned embodiments likewise applies to semiconductor chip 2004and the insulating layer 2001.

An electrically conductive layer structured into one or more conductortrack 2003 and an electrical contact pad 2050 may be arranged over theinsulating layer 2001. The electrically conductive layer may be made ofan electrically conducting material such as, e.g., a metal, a metalalloy, solder, or an electrically conducting polymer. The electricalcontact pad 2050 and the one or more conductor tracks 2003 connected tothe electrical contact pad 2050 may extend directly on the upper surface2002 of insulating layer 2001.

A dielectric layer 2030 may be arranged over the conductive layer ofwhich the electrical contact pad 2050 and the one or more conductortracks 2003 are formed. The dielectric layer 2030 may have an opening todefine and expose the electrical contact pad 2050. Thus, the dielectriclayer 2030 may serve as a solder stop layer. It may be made of the samematerial(s) as the dielectric layer of the aforementioned embodimentsand as the insulating layer 2001. The conductor track(s) 2003, theinsulating layer 2001, the electrical contact pad 2050 and thedielectric layer 2030 may each be in direct contact to the respectiveadjacent layer(s) or structures, or may be separated by intermediatelayers such as, e.g., adhesion layers, or by multiple polymer and/orconductive layers of a multi-layer RDL from the respective adjacentlayer(s) or structures. In other words, the insulating layer 2001 (e.g.,a polymer layer) and the conductive layer (e.g., a metal layer)structured to the electrical contact pad 2050 and conductor tracks 2003may form part of an RDL which may comprise a stack of multiplealternating insulating layers 2001 and conductive layers.

A solder deposit 2060 such as, e.g., a solder bump or solder ball may beattached to the electrical contact pad 2050. The solder deposit 2060 mayrepresent an external terminal of a package accommodating the structure2070. The dimensions, materials and characteristics of solder deposit2060 may be the same as mentioned herein before with respect toembodiments.

FIG. 12 is a schematic top view of electrical device 2000. FIG. 12illustrates an interconnection between conductor track 2003 and theelectrical contact or bond pad 2050 of electrical device 2000. Conductortrack 2003 may have an elongated line section 2003 a. The conductortrack 2003 has a branching A. The branching A partitions the conductortrack 2003 into at least two conductor track branches with each of theat least two conductor track branches connecting to the electricalcontact pad 2050 at a different location. In FIG. 12 three conductortrack branches 2003_1, 2003_2, 2003_2′ are illustrated with conductortrack branch 2003_1 connecting to the electrical contact pad 2050 at B1,conductor track branch 2003_2 connecting to the electrical contact pad2050 at B2 and conductor track branch 2003_2′ connecting to theelectrical contact pad 2050 at B2′. As illustrated by way of example inFIG. 12, the electrical contact pad 2050 may have a substantiallyrounded shape. Further, the locations B1, B2, B2′ may be approximatelyequidistantly distributed around the periphery of the electrical contactpad 2050.

The length of conductor track branch 2003_1 as measured between A and B1is smaller than each of the lengths of the conductor track branches2003_2, 2003_2′ as measured between A and B2 and A and B2′,respectively. Further, the (minimum) width WR2 of conductor track branch2003_2 and the (minimum) width WR2′ of conductor track branch 2003_2′are greater than the (minimum) width WR1 of conductor track branch2003_1. The widths of conductor track branches 2003_1, 2003_2 and2003_2′ may each be approximately constant over their lengths. Further,in the example shown, WR2 may be equal to WR2′.

In other words, the shorter the conductor track branch, the smaller the(minimum) width thereof. That way, the (sheet) current densities at thelocations B1, B2, B2′ hitting the electrical contact pad 2050 are only afraction (here about ⅓) of the current density which would hit theelectrical contact pad 2050 if only one conductor track branch (e.g.,conductor track branch 2003_1) would be provided. By way of example,given a current of about 100 mA in the conductor track 2003, the maximumsheet current density hitting the electrical contact pad 2050 could bereduced from about 30 A/mm² to about 10 A/mm². Further, by designing the(minimum) width of the conductor track branches 2003_1, 2003_2, 2003_2′in accordance with the rule stated above, it is always possible toprovide for approximately equal (sheet) current densities at thelocations B1, B2 and B2′.

More specifically, the condition of equal (sheet) current densities atthe locations B1, B2 and B2′ is approximately satisfied if theelectrical resistances of the conductor track branches 2003_1, 2003_2and 2003_2′ are equal. That way, electromigration at the locations B1,B2 and B2′ is minimized.

FIG. 13 illustrates a schematic top view of an interconnection betweenconductor track 2003 and an electrical contact (or bond) pad 2050 ofelectrical device 2000 in accordance with one embodiment. The electricaldevice 2000 shown in FIG. 13 may be implemented similar to theelectrical device 2000 shown in FIGS. 11 and 12. In FIG. 13, the linesection 2003 a of conductor track 2003 splits into an number of 13conductor track branches, with the conductor track branches in the upperhalf of FIG. 13 being designated by reference numerals 2003 _(—) n, n=1,2, . . . , 7. Similar to electrical device 2000 as shown in FIG. 12, thelonger the conductor track branches 2003 _(—) n as measured frombranching A to Bn, respectively, the greater the width thereof. Further,the electrical resistance of all conductor track branches 2003 _(—) nmay be approximately the same. That way, the current flowing from orinto the conductor track 2003 is approximately uniformly distributedover the circumference of the contact pad, either over the fullcircumference or over a portion of, e.g., at least ½, ⅔ or ¾ of thecircumference of the electrical contact pad 1150 (corresponding toelectrical contact pad 2050).

It is to be noted that a plurality of branchings A at differentlocations rather than a single common branching A as depicted by way ofexample in FIGS. 12 and 13 may be provided. Further, the electricaldevice 2000 concerning the interconnection of a conductor track to anelectrical contact pad may be implemented in combination with theelectrical devices 100 to 1000 concerning the interconnection of arouting line to a via. In other embodiments, the electrical device 2000concerning the interconnection of a conductor track to an electricalcontact pad may not be implemented in combination with aninterconnection of a conductor track to a via as exemplified byelectrical devices 100 to 1000.

According to FIG. 14, a method of manufacturing an electrical deviceaccording to embodiments as illustrated in FIGS. 1 to 10 comprises thestep S1 of providing a semiconductor chip, the semiconductor chipcomprising a routing line.

At step S2, an insulating layer over the semiconductor chip is formed,the insulating layer having an opening.

At step S3, a via extending through the opening of the insulating layerto electrically connect to the routing line is formed. The via isdesigned such that a front edge line portion of the via facing therouting line is substantially straight, has a concave curvature or has aconvex curvature of a diameter greater than a maximum lateral dimensionof the via (or, e.g., of the routing line or, e.g., of the solderdeposit).

At step S4, a solder deposit is placed over the insulating layer toelectrically connect to the via.

According to FIG. 15, a method of manufacturing an electrical deviceaccording to embodiments as illustrated in FIGS. 11 to 13 comprises thestep S1′ of providing an insulating layer having a first surface.

At step S2′ an electrical contact pad is formed on the first surface ofa structure.

Concurrently, before or after step S2′, at least one conductor trackextending on the first surface is formed (step S3′).

At step S4′, the conductor track is connected to the electrical contactpad via at least two conductor track branches dividing the conductortrack at a branching and connecting to the electrical contact pad atdifferent locations. Step S4′ may be accomplished concurrently or afterthe steps S2′ and/or S3′. Further, in one embodiment, a solder depositmay then be placed on the electrical contact pad.

In addition, while a particular feature or aspect of an embodiment ofthe invention may have been disclosed with respect to only one ofseveral implementations, such feature or aspect may be combined with oneor more other features or aspects of the other implementations as may bedesired and advantageous for any given or particular application. By wayof example, the design of the conductor tracks 2003 as illustrated inFIGS. 12 and 13 may also apply as a further design of the routing lines103-1003 as depicted in FIGS. 1 to 10. Furthermore, to the extent thatthe terms “include”, “have”, “with”, or other variants thereof are usedin either the detailed description or the claims, such terms areintended to be inclusive in a manner similar to the term “comprise”.Furthermore, it should be understood that embodiments of the inventionmay be implemented in discrete circuits, partially integrated circuitsor fully integrated circuits or programming means. Also, the term“exemplary” is merely meant as an example, rather than the best oroptimal. It is also to be appreciated that features and/or elementsdepicted herein are illustrated with particular dimensions relative toone another for purposes of simplicity and ease of understanding, andthat actual dimensions may differ substantially from that illustratedherein.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. An electrical device comprising: a semiconductorchip, the semiconductor chip comprising a horizontal routing line,wherein the routing line comprises a contact section and a line sectionelectrically coupled to the contact section and extending laterally fromthe contact section; an insulating layer arranged over the semiconductorchip; a solder deposit arranged over the insulating layer; and a viaextending through an opening in the insulating layer to electricallyconnect the contact section to the solder deposit, wherein a horizontalfront edge line portion of the via laterally facing the line section issubstantially straight, has a concave curvature or has a convexcurvature of a diameter greater than a maximum lateral dimension of thevia.
 2. The electrical device of claim 1, wherein the front edge lineportion of the via has a length measured between two bends of the frontedge line, the length being greater than 100 μm.
 3. The electricaldevice of claim 1, wherein a cross-section of the via through an uppersurface of the insulating layer has one of a rectangular, triangular,oval or half-round shape.
 4. The electrical device of claim 1, furthercomprising an electrically conductive layer arranged over the insulatinglayer, the electrically conductive layer forming an electrical contactpad for the solder deposit.
 5. The electrical device of claim 1, whereinthe insulating layer comprises one or both of a hard passivation layerand a polymer layer.
 6. The electrical device of claim 1, wherein thefront edge line portion of the via has a convex curvature of a diametergreater than a maximum lateral dimension of the routing line or of adiameter greater than a maximum lateral dimension of the solder deposit.7. The electrical device of claim 1, further comprising multiple viasextending through multiple openings in the insulating layer toelectrically connect the routing line to the solder deposit, wherein themultiple vias are arranged in a pattern, an outline of the patterndefining a front edge pattern line portion that is orientedsubstantially perpendicular to a longitudinal direction of the routingline.
 8. The electrical device of claim 4, wherein the electricallyconductive layer has a thickness that is smaller than 10 μm.
 9. Theelectrical device of claim 4, wherein the electrically conductive layerfills the opening of the insulating layer to form the via.
 10. Anelectrical device comprising: a semiconductor chip, the semiconductorchip comprising a routing line, wherein the routing line comprises acontact section and a line section electrically coupled to the contactsection and extending laterally from the contact section; an insulatinglayer arranged over the semiconductor chip; a first solder depositarranged over the insulating layer; and multiple vias extending throughmultiple openings in the insulating layer to electrically connect thecontact section to the first solder deposit, wherein the multiple viasare arranged in a spatial pattern of vias, an outline of the patterndefining a front edge pattern line portion that is orientedsubstantially perpendicular to a longitudinal direction of line section.11. The electrical device of claim 10, wherein the front edge patternline portion of the outline of the pattern has a concave or straightshape.
 12. The electrical device of claim 10, wherein a front edge lineportion of a via of the multiple vias facing the routing line issubstantially straight, has a concave curvature or has a convexcurvature of a diameter greater than a maximum lateral dimension of thevia.
 13. The electrical device of claim 12, wherein the front edge lineportion of the via has a length measured between two bends of the frontedge line, the length being greater than 100 μm.